64k x 4 static ram with separate i/o cy7c192 cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-05047 rev. *b revised january 6, 2006 features ?high speed ?12 ns ? cmos for optimum speed/power ? low active power ?880 mw ? low standby power ?220 mw ? ttl-compatible inputs and outputs ? automatic power-down when deselected functional description the cy7c192 is a high-perf ormance cmos static ram organized as 65,536 x 4 bits with separate i/o. easy memory expansion is provided by active low chip enable ( ce ) and three-state drivers. it has an automatic power-down feature, reducing the power consumption by 75% when deselected. writing to the device is accomplished when the chip enable ( ce ) and write enable ( we ) inputs are both low. data on the four input pins (i 0 through i 3 ) is written into the memory location specified on the address pins (a 0 through a 15 ). reading the device is accomplished by taking the chip enable ( ce ) low while the write enable ( we ) remains high. under these conditions the contents of the memory location specified on the address pins will appear on the four data output pins. the output pins stay in high-impedance state when write enable ( we ) is low, or chip enable ( ce ) is high. a die coat is used to insure alpha immunity. gnd 28 logic block diagram pin configurations 1024 x 64 x 4 array a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 10 a 11 a 13 a 12 a 14 a 15 column decoder row decoder sense amps power down we o 0 ce o 1 o 2 o 3 4 5 6 7 8 9 10 321 27 1314151617 26 25 24 23 22 21 20 1 2 3 4 5 6 7 8 9 10 11 14 15 16 20 19 18 17 21 24 23 22 top view dip/soj a 6 a 7 a 8 a 9 a 10 a 11 a 12 a 13 we v cc a 4 a 3 a 2 a 1 o 3 o 2 o 1 o 0 a 0 ce 11 12 19 18 a 8 v cc a 9 a 10 a 11 a 12 a 13 a 14 a 15 i 0 a 4 a 3 a 2 a 1 a 0 i 3 i 2 o 3 o 1 gnd ce we top view lcc 12 13 input buffer 25 28 27 26 a 14 a 15 i 0 i 1 a 5 i 3 i 2 i 1 a 7 a 6 a 5 o 2 o 0 i 0 i 1 i 2 i 3 a 0 a 9 selection guide 7c192-12 7c192-15 7c192-20 7c192-25 unit maximum access time 12 15 20 25 ns maximum operating current 155 145 135 115 ma maximum standby current 30 30 30 30 ma
cy7c192 document #: 38-05047 rev. *b page 2 of 10 maximum ratings (above which the useful life may be impaired. for user guide - lines, not tested.) storage temperature ..................................... ? 65 c to +150 c ambient temperature with power applied .................................................. ? 55 c to +125 c supply voltage to ground potential (pin 28 to pin 14) .................................................? 0.5v to +7.0v dc voltage applied to outputs in high z state [ 1 ] ........................................ ? 0.5v to v cc + 0.5v dc input voltage [ 1 ] .................................... ? 0.5v to v cc + 0.5v output current into outputs (low)............................. 20 ma static discharge voltage............................................. >900v (per mil-std-883, method 3015) latch-up current .................................................... >200 ma operating range range ambient temperature [ 2 ] v cc commercial 0 c to +70 c 5v 10% electrical characteristics over the operating range parameter description test conditions 7c192-12 7c192-15 min. max. min. max. unit v oh output high voltage v cc = min., i oh = ? 4.0 ma 2.4 2.4 v v ol output low voltage v cc = min., i ol = 8.0 ma 0.4 0.4 v v ih input high voltage 2.2 v cc + 0.3v 2.2 v cc + 0.3v v v il input low voltage [ 1 ] ? 0.5 0.8 ? 0.5 0.8 v i ix input load current gnd < v i < v cc ? 5 +5 ? 5 +5 a i oz output leakage current gnd < v o < v cc , output disabled ? 5 +5 ? 5 +5 a i os output short circuit current [ 3 ] v cc = max., v out = gnd ? 300 ? 300 ma i cc v cc operating supply current v cc = max. , i out = 0 ma, f = f max = 1/t rc 155 145 ma i sb1 automatic ce power-down current? ttl inputs max. v cc , ce > v ih , v in > v ih or v in < v il , f = f max 30 30 ma i sb2 automatic ce power-down current?cmos inputs max. v cc , ce > v cc ? 0.3v, v in > v cc ? 0.3v or v in < 0.3v, f = 0 10 10 ma notes: 1. minimum voltage is equal to ?2.0v for pulse durations of less than 20 ns. 2. t a is the case temperature. 3. not more than 1 output should be shorted at one time. dura tion of the short circuit shou ld not exceed 30 seconds.
cy7c192 document #: 38-05047 rev. *b page 3 of 10 electrical characteristics over the operating range parameter description test conditions 7c192-20 7c192-25 min. max. min. max. unit v oh output high voltage v cc = min., i oh = ? 4.0 ma 2.4 2.4 v v ol output low voltage v cc = min., i ol = 8.0 ma 0.4 0.4 v v ih input high voltage 2.2 v cc + 0.3v 2.2 v cc + 0.3v v v il input low voltage [ 1 ] ? 0.5 0.8 ? 3.0 0.8 v i ix input load current gnd < v i < v cc ? 5 +5 ? 5 +5 a i oz output leakage current gnd < v o < v cc , output disabled ? 5 +5 ? 5 +5 a i os output short circuit current [ 3 ] v cc = max., v out = gnd ? 300 ? 300 ma i cc v cc operating supply current v cc = max. , i out = 0 ma, f = f max = 1/t rc 135 115 ma i sb1 automatic ce power-down current?ttl inputs max. v cc , ce > v ih , v in > v ih or v in < v il , f = f max 30 30 ma i sb2 automatic ce power-down current?cmos inputs ce > v cc ? 0.3v, v in v cc ? 0.3v or v in < 0.3v, f = 0 15 15 ma capacitance [ 4 ] parameter description test conditions max. unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 5.0v 8 pf c out output capacitance 10 pf ac test loads and waveforms [ 5 ] notes: 4. tested initially and after any design or proc ess changes that may affect these parameters. 5. t r = < 3 ns for the -12 and -15 speeds. t r = < 5 ns for the -20 and slower speeds. 3.0v 5v output r1 481 ? r2 255 ? 30 pf including jig and scope gnd 90% 10% 90% 10% < t r < t r 5v output r1 481 ? r2 255 ? 5pf including jig and scope (a) (b) output 1.73v equivalent to: th venin equivalent all input pulses 167 ?
cy7c192 document #: 38-05047 rev. *b page 4 of 10 switching characteristics over the operating range [ 6 ] 7c192-12 7c192-15 7c192-20 7c192-25 parameter description min. max. min. max. min. max. min. max. unit read cycle t rc read cycle time 12 15 20 25 ns t aa address to data valid 12 15 20 25 ns t oha output hold from address change 3 3 3 3 ns t ace ce low to data valid 12 15 20 25 ns t lzce ce low to low z [ 7 ] 3 3 3 3 ns t hzce ce high to high z [ 7 , 8 ] 5 7 9 11 ns t pu ce low to power-up 0 0 0 0 ns t pd ce high to power-down 12 15 20 25 ns write cycle [ 9 ] t wc write cycle time 12 15 20 25 ns t sce ce low to write end 9 10 15 18 ns t aw address set-up to write end 9 10 15 20 ns t ha address hold from write end 0 0 0 0 ns t sa address set-up to write start 0 0 0 0 ns t pwe we pulse width 8 9 15 18 ns t sd data set-up to write end 8 9 10 10 ns t hd data hold from write end 0 0 0 0 ns t lzwe we high to low z [ 7 ] 3 3 3 3 ns t hzwe we low to high z [ 7 , 8 ] 7 7 10 11 ns notes: 6. test conditions assume signal transition time of 3 ns or less for -12 and -15 speeds and 5 ns or less for -20 through -25 spe eds, timing reference levels of 1.5v, input pulse levels of 0 to 3.0v, and output loading of the specified i ol /i oh and 30-pf load capacitance. 7. at any given temperature and voltage condition, t hzce is less than t lzce , t hzw\e is less than t lzwe for any given device. these parameters are guaranteed by design and not 100% tested. 8. t hzce and t hzwe are specified with c l = 5 pf as in part (b) of ac test loads. transition is measured 500 mv from steady-state voltage. 9. the internal write time of the memory is defined by the overlap of ce low and we low. both signals must be low to initiate a write and either signal can terminate a write by going high. the data input set-up and hold timing should be referenced to the rising edge of the signal th at terminates the write.
cy7c192 document #: 38-05047 rev. *b page 5 of 10 switching waveforms read cycle no. 1 [ 10 , 11 ] read cycle no. 2 [ 10 , 12 ] write cycle no. 1 ( we controlled) [ 9 ] notes: 10. we is high for read cycle. 11. device is continuously selected, ce = v il . 12. address valid prior to or coincident with ce transition low. address data out previous data valid data valid t rc t aa t oha 50% 50% data valid t rc t ace t lzce t pu data out high impedance impedance icc isb t hzce t pd ce high v cc supply current t wc data valid data undefined high impedance t sce t aw t sa t pwe t ha t hd t hzwe t lzwe t sd ce we data in data out address
cy7c192 document #: 38-05047 rev. *b page 6 of 10 write cycle no. 2 ( ce controlled) [ 9 , 13 ] note: 13. if ce goes high simultaneously with we high, the output remains in a high-impedance state. switching waveforms (continued) t wc data valid t sce t aw t sa t pwe t ha t hd t sd high impedance t hzwe address ce we data in data out
cy7c192 document #: 38-05047 rev. *b page 7 of 10 typical dc and ac characteristics 1.2 1.4 1.0 0.6 0.4 0.2 4.0 4.5 5.0 5.5 6.0 1.6 1.4 1.2 1.0 0.8 -55 25 125 ?55 25 125 1.2 1.0 0.8 normalized t aa 120 100 80 60 40 20 0.0 1.0 2.0 3.0 4.0 output source current (ma) supply voltage (v) normalized supply current vs. supply voltage normalized access time vs. ambient temperature ambient temperature ( c) normalized supply current vs. ambient temperature ambient temperature( c) output voltage (v) output source current vs. output voltage 0.0 0.8 1.4 1.1 1.0 0.9 4.0 4.5 5.0 5.5 6.0 normalized t supply voltage ( v ) normalized access time vs. supply voltage 120 140 100 60 40 20 0.0 1.0 2.0 3.0 4.0 output sink current (ma) 0 80 output voltage (v) output sink current vs. output voltage 0.6 0.4 0.2 0.0 normalized i, i cc sb normalized i, i cc sb i sb i cc i cc v cc =5.0v v cc =5.0v t a =25 c v cc =5.0v t a =25 c i sb t a =25 c 0.6 0.8 0 aa 1.3 1.2 v in =5.0v t a =25 c 1.4 v cc =5.0v v in =5.0v 3.0 2.5 2.0 1.5 1.0 0.5 0.0 1.0 2.0 3.0 4.0 normalized i po supply voltage (v) typical power-on current vs. supply voltage 30.0 25.0 20.0 15.0 10.0 5.0 0 200 400 600 800 delta t (ns) aa capacitance (pf) typical access time change vs. output loading 1.25 1.00 0.75 10 20 30 40 normalized i cc cycle frequency (mhz) normalized i cc vs. cycle time 0.0 5.0 0.0 1000 0.50 v cc =4.5v t a =25 c v cc =5.0v t a =25 c v in =0.5v
cy7c192 document #: 38-05047 rev. *b page 8 of 10 ordering information speed (ns) ordering code package diagram package type operating range 12 cy7c192-12pc 51-85014 28-lead (300-mil) molded dip commercial cy7c192-12vc 51-85031 28-lead molded soj 15 cy7c192-15pc 51-85014 28-lead (300-mil) molded dip commercial cy7c192-15vc 51-85031 28-lead molded soj 20 cy7c192-20pc 51-85014 28-lead (300-mil) molded dip commercial cy7c192-20vc 51-85031 28-lead molded soj 25 CY7C192-25PC 51-85014 28-lead (300-mil) molded dip commercial cy7c192-25vc 51-85031 28-lead molded soj cy7c192-25vxc 51-85031 28-lead molded soj (pb-free) package diagrams dimensions in inches [mm] min. max. seating plane 0.260[6.60] 0.295[7.49] 0.090[2.28] 0.110[2.79] 0.055[1.39] 0.065[1.65] 0.015[0.38] 0.020[0.50] 0.015[0.38] 0.060[1.52] 0.120[3.05] 0.140[3.55] 0.009[0.23] 0.012[0.30] 0.310[7.87] 0.385[9.78] 0.290[7.36] 0.325[8.25] 0.030[0.76] 0.080[2.03] 0.115[2.92] 0.160[4.06] 0.140[3.55] 0.190[4.82] 1.345[34.16] 1.385[35.18] 3 min. 1 14 15 28 reference jedec mo-095 lead end option see lead end option see lead end option (lead #1, 14, 15 & 28) package weight: 2.15 gms 28-lead (300-mil) pdip (51-85014) 51-85014-*d
cy7c192 document #: 38-05047 rev. *b page 9 of 10 ? cypress semiconductor corporation, 2006. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. all products and company names mentioned in this docum ent may be the trademarks of their respective holders. package diagrams (continued) min. max. pin 1 id 0.291 0.300 0.050 typ. 0.007 0.013 0.330 0.350 0.120 0.140 0.025 min. 0.262 0.272 0.697 0.713 0.013 0.019 0.014 0.020 0.032 0.026 a a detail external lead design option 1 option 2 1 14 15 28 0.004 seating plane note : 1. jedec std ref mo088 2. body length dimension does not include mold protrusion/end flash mold protrusion/end flash shall not exceed 0.006 in (0.152 mm) per side 3. dimensions in inches 51-85031-*c 28-lead (300-mil) molded soj (51-85031)
cy7c192 document #: 38-05047 rev. *b page 10 of 10 document history page document title: cy7c192 64k x 4 static ram with separate i/o document number: 38-05047 rev. ecn no. issue date orig. of change description of change ** 107149 09/10/01 szv change spec number from: 38-00076 to 38-05047 *a 359716 see ecn aju changed static discharge voltage limit in the maximum ratings section (page 2) from 2001v to 900v removed references to cy7c191. *b 419549 see ecn aju added pb-free parts to the ordering information table and replaced the package name column with package diagram
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